With the increasing down scaling of integrated circuits and increasingly higher requirements for integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFETs) were thus developed.
Similar to planar transistors, source and drain silicides may be formed on the source and drain regions of FinFETs. However, since the fins of FinFETs are typically narrow, current crowding may occur. In addition, it is difficult to land contact plugs onto the source/drain portions of fins. Epitaxy semiconductor layers are thus formed on the fins to increase their volumes using epitaxy processes.
The epitaxial processes, however, suffer from drawbacks. FIG. 1 illustrates a cross-sectional view of a semiconductor structure including source/drain region 2 (which is part of the original fin) and epitaxy layer 4 epitaxially grown on source/drain region 2. In contrast to conventional planar devices, the volumes of source/drain regions 2 are not confined by shallow trench isolation (STI) regions 6. Since epitaxy layer 4 may have a growth rate smaller on (111) planes than on other planes, the outer surface of epitaxy layer 4 may not have a rectangular (or near-rectangular) profile as that of the original fin 2. Instead, epitaxy layer 4 may extend laterally and form facets 8. This may cause the excess reduction in the distance between epitaxy layers grown from neighboring fins. Accordingly, the merging window, in which the epitaxy layers growing from neighboring fins will not merge, is reduced. Further, even if the neighboring epitaxy layers 4 belong to a source/drain region of a same multi-fin FinFET, void 10 will be undesirably generated as a result of the merging of epitaxy layers 4 grown from neighboring fins 2, as shown in FIG. 2.